Chip Gallery

Disclaimer: most of these references are the effect of the point of view of myself, Francesco Conti, maintainer and dictator of this site. Most chips shown here are related to work on HWPEs performed in the context of the PULP project during my activity at University of Bologna (2012-ongoing) and ETH Zurich (2015-2020). Although there is a Other authors section, there may be several missing chips using the HWPE IPs and/or a similar template. In case you spot a missing reference, let me know.

PULP chips

Table 90 PULP chips

Chip	Year	Notes
Megatron	2024	PULP cluster with Softex, other accelerator.
Astral http://asic.ethz.ch/2024/Astral.html	2024	PULP cluster with NEureka, RedMulE, Softex.
Maestro http://asic.ethz.ch/2023/Maestro.html	2023	PULP cluster with RedMulE integrated with Spatz.
Siracusa http://asic.ethz.ch/2022/Siracusa.html	2022	PULP cluster with NEureka and MRAM integration.
Darkside http://asic.ethz.ch/2021/Darkside.html	2021	PULP cluster with RedMulE, DepthWise Engine, DataMover Engine
Echoes http://asic.ethz.ch/2021/Echoes.html	2021	PULPissimo with FFT HWPE
Kraken http://asic.ethz.ch/2021/Kraken.html	2021	PULP cluster with SNE and PULPO (they do not directly use HWPE IPs, but they follow the same HWPE template)
Marsellus http://asic.ethz.ch/2021/Marsellus.html	2021	PULP cluster with RBE (pulp-platform/rbe)
Vega http://asic.ethz.ch/2020/Vega.html	2020	PULP cluster with HWCE v4
Xavier http://asic.ethz.ch/2019/Xavier.html	2019	PULPissimo with QNE
Poseidon (Quentin) http://asic.ethz.ch/2018/Poseidon.html	2019	Chip including a PULPissimo with XNE
GAP8 http://asic.ethz.ch/2017/GAP8.html	2017	Commercial SoC including HWCE v3
Fulmine http://asic.ethz.ch/2015/Fulmine.html	2015	PULP cluster design with HWCE v2, HWCrypt (the latter follows the HWPE template but does not use HWPE IPs)
Mia Wallace http://asic.ethz.ch/2015/Mia_Wallace.html	2015	PULP cluster design with HWCE v1
PULP3 http://asic.ethz.ch/2015/Pulpv3.html	2015	PULP cluster design with HWCE v1